Plan now to join us for free technical sessions, free lunch and the chance to network with leading suppliers to our industry!
Free Technical Program & Schedule:
9:15AM – 10:00AM
Understanding PCB Design & Material Warpage Challenges Which Occur During B2B Board-to-Board/Module-Carrier Attachment
Speaker: Eric Moen, Akrometrix
PCB warpage has been identified as one of several key contributors to unacceptable yield rates during reflow assembly of a PCB module to a PCB carrier board. The module has a land grid array pattern and is placed directly on solder paste on the carrier board. This results in low-profile solder joints which are sensitive to the co-planarity of both the module and the carrier boards. The typical failure mode occurs when one or more solder joint opens are caused by a lifted corner of the module during/after reflow.
In an effort to improve attachment yield rates, a design of experiment has been proposed to evaluate several PCB design variables that are believed to contribute to warpage during reflow, including: (1) laminate material, (2) layer-to-layer copper balance, (3) panel configuration of the 6-up module array and (4) location of the 6-up array in the PCB fabricator’s working panel. To simplify the investigation, only the variables associated with module PCBs are considered; the carrier PCB design is held constant.
Additional graphical and statistical data which shows real-time at-temperature warpage behavior of several PCB modules and carriers will also be presented. This includes a detailed at-temperature gap analysis which shows the co-planarity gap between module and carrier at each critical reflow temperature.
This paper & presentation will present graphical and statistical details of at-room-temperature metrology on a large sample of modules with differing design variables. Shadow Moiré technique will be used to provide accurate warpage profiles of the 6-up module arrays before and after top- and bottom-side assembly, and again before and after attachment to the carrier board. A large volume of samples will be tested in order to gain statistical relevance of the data and correlate any yield problems to initial warpage. The objective is to isolate the key design parameter(s) that contribute most to attachment problems while also observing & reporting on the at-temperature warpage behavior of the substrates during reflow.
11:00AM – 11:45AM
Wearable Electronics Drives a New Manufacturing Paradigm!
Speaker: Charles Bauer, Ph.D., TechLead Corporation
With all the excitement around IoT (Internet of Things), big data and cognitive computing the impact of wearable electronics and smart textiles on the manufacturing environment frequently gets lost in the noise. However, these trends create many new and exciting challenges for the electronics industry, including new design, manufacture, test, and supply chain paradigms. The central role played by sensors, energy storage and energy harvest devices results in altogether revolutionary packaging concerns. Intended for intimate contact with human skin in diverse, often hostile environments such as automobile cabins and seawater, these systems require new yet proven safe and reliable materials as well as customized application configurations. This presentation explores the seemingly conflicting requirements of achieving low cost while meeting the high volume, high mix product requirements of this brave new world of electronics systems.
1:00PM – 1:45PM
Equipment Road Maps… A Guide to Planning in the SMT Environment
Speaker: David Nixon, Keytronic EMS
Do you find yourself reacting to new production equipment needs that you didn’t budget for? Often finding yourself struggling to find the right equipment with room for production expansion. This presentation will walk you through the process of building a 5-year equipment road map so that your budget and equipment needs are planned and not reactionary. We will discuss several methods for growth projection and the in’s and out of new vs used equipment.
2:30PM – 3:15PM
Establishing DFM Guidelines on Discrete Component Spacing in Printed Circuit Board Assembly
Speaker: John Harrell, Micron Technology, Inc.
Surface mount technology (SMT) is ubiquitous in electronics industry. The solder paste printing and placement process forms the core of SMT technology. With increasing customer demands for small form factor in high-capacity memory, space in a printed circuit board (PCB) is premium; and, hence, careful consideration must be given to PCB design. In the current PCB design for manufacturing (DFM) guidelines, discrete component spacing rule is defined without considering package size combinations. The key objective of this study is to propose new spacing between land pads for discrete components like resistors and capacitors in PCB design. This proposal enables smaller form factor in high-capacity memory. Screening, optimization experiments, and analyses were performed to substantiate the proposal.
Drawing for Door Prizes - Must be present to win!