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Solder Pad Cratering Webtorial

Presenter: Cheryl Tulkoff
Company: DfR Solutions
Date Published: 4/12/2012

Description: Pad cratering is defined as cracking which initiates within the laminate during a dynamic mechanical event such as In Circuit Testing (ICT), board depanelization, connector insertion, and other shock and vibration inducing activities. During this webtorial, you'll learn the key drivers, measurement and detection protocols, and preventive tactics for this serious but prevalent failure. Pad cratering was first recognized in BGA packages but newer leadless, bottom termination components are also vulnerable.

Topics Covered:
  • Pad Cratering Defined
  • Is Pad Cratering a Pb-free issue?
  • At risk components
  • Drivers
  • Finer pitch components
  • More brittle laminates
  • Stiffer solders (SAC vs. SnPb)
  • Presence of a large heat sink
  • Detection and Failure Analysis Procedures: Which ones are effective & why
  • X-ray
  • Dye-n-pry
  • Ball shear
  • Ball pull
  • Mitigation Practices & Solutions to Pad Cratering
  • Board Redesign
  • Solder mask defined vs. non-solder mask defined
  • Limitations on board flexure
  • 750 to 500 microstrain, Component dependent
  • Specification and Procedure Discussion
  • Strain Gage Testing Protocols
  • ICT Fixture Evaluation
  • Assembly Process Evaluation
  • Process Specifications
  • More compliant solder
  • SAC305 is relatively rigid, SAC105 and SNC are possible alternatives
  • New acceptance criteria for laminate materials
  • Intel-led industry effort
  • Attempting to characterize laminate material using high-speed ball pull and shear testing, Results inconclusive to-date
  • Alternative approaches
  • Require reporting of fracture toughness and elastic modulus

    Targeted Audience:
    Design, Manufacturing, and Failure Analysis Engineering

    Instructor Bio:
    Cheryl Tulkoff is an industry renowned expert in the fields of semiconductor fabrication, electronics assembly, RoHS conversion, and reliability engineering and management. Prior to joining DfR, Ms. Tulkoff had an active leadership role both within her employer's companies and among regional and national electronics and reliability organizations. At her most recent position at National Instruments, Cheryl developed a comprehensive reliability organization, including the creation of an internal failure analysis group and a closed loop reliability program. She has also taken the lead in process development and implementation in semiconductor fabrication through her work at Cypress Semiconductor in electronics assembly, and through her work at IBM. Cheryl is the head of DfR's office located in Austin, Texas, which opened in February 2009. B.S., Mechanical Engineering (Georgia Institute of Technology)

  • Key Words: 

    solder pad cratering, ICT, depanelization



    Pricing:
      Members: $200.00 (Log on to receive the member rate)
      Non-Members: $300.00



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