International Wafer Level Packaging Congress 2004 Proceedings

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TITLE AUTHOR
APPLICATIONS FOR SILICON MICROMACHINING IN ADVANCED DEVICE PACKAGING SCHEMES A.A. Chambers  Abstract
KEY ASSEMBLY TECHNOLOGY FOR 3D PACKAGING - STACKED-DIE AND STACKED PACKAGE Akito Yoshida et al.  Abstract
THROUGH-MASK ELECTRODEPOSITION OF LEADFREE SOLDERS FOR WAFER-LEVEL PACKAGING APPLICATIONS B. Kim, T. Ritzdorf, D. Schmauch, and P. Siblerud  Abstract
WAFER THINNING WITH THE 3M WAFER SUPPORT SYSTEM Carl R. Kessel et al.  Abstract
LOW COST FLIP CHIP SOLUTIONS, C3 AND BEYOND Charles E. Bauer, Ph.D. / Alexander Taran  Abstract
YIELD MODEL FOR ASSEMBLY OF AREA ARRAY SOLDER INTERCONNECT PACKAGES WITH EXPERIMENTAL VERIFICATION Chunho Kim, Ph.D. / Daniel F. Baldwin, Ph.D.  Abstract
WAFER LEVEL MEMS PACKAGING STRATEGIES Daniel F. Baldwin, Ph.D.  Abstract
FLEXIBLE FLIP CHIP CONNECTION Donald G. McBride and Ronald Blankenhorn  Abstract
DETECTING AND ANALYZING WAFER BUMP VOIDS WITH X-RAY INSPECTION Dr. Udo E. Frank  Abstract
TRENDS IN IC ASSEMBLY AND PACKAGING E. Jan Vardaman and Linda Matthew  Abstract
MAIN PROGRESS ON WAFER LEVEL PACKAGING FOR SMART CARD, RF AND 3D APPLICATIONS Gilles Poupon  Abstract
LEAD-FREE IS NOT ALPHA-FREE - WHY WLCSPS SHOULD CARE ABOUT ALPHA PARTICLES Glenn A. Rinne and Krishna K. Nair  Abstract
STACKED DIE AND 3-D DESIGN TOOLS Gordon Jensen  Abstract
NOVEL LEAD-FREE WAFER-LEVEL UNDERFILL MATERIALS FOR CHIPSCALE PACKAGING Gyan Dutt et al.  Abstract
WAFER LEVEL PACKAGING: CURRENT SOLUTIONS AND DEVELOPING TRENDS H. Balkan et al.  Abstract
VOID-FREE BUMPING PROCESS FOR LEAD-FREE SOLDER J. Yoshioka et al.  Abstract
WAFER LEVEL BURN-IN & TEST USING SACRIFICIAL METAL AS AN INTERFACE MEDIUM John Darling  Abstract
DEVELOPMENT OF TRANSMISSION LASER BONDING TECHNIQUE FOR WAFER-LEVEL MEMS PACKAGING Jong-Seung Park and Ampere A. Tseng  Abstract
PHOTO LITHOGRAPHY PROCESSES ON SEVERE TOPOGRAPHY FOR WAFER LEVEL PACKAGING APPLICATIONS K. Fischer, D. Tönnies and R. Süss  Abstract
LASER CLOSING OF WINDOW AS A NOVEL WAFER-LEVEL HERMETIC PACKAGING TECHNOLOGY K. P. Cheung and Y. Wang et al.  Abstract
KNOWN GOOD DIE FOR WAFER LEVEL PACKAGING Larry Gilg  Abstract
SINGLE WAFER APPROACH FOR 300 mm FOR UNDER BUMP METAL ETCHING Lucy Chen, David Chen, and Jackie Chen  Abstract
SHELLCASE-TYPE WAFER-LEVEL PACKAGING SOLUTIONS: RF CHARACTERIZATION AND MODELING M. Bartek et al.  Abstract
EVOLUTION OF WLP: FROM REDISTRIBUTION TO 3-D PACKAGING AND MEMS PACKAGING M. Töpper et al.  Abstract
PRESENTING DIE TO A PICK-AND-PLACE MACHINE AT 3,000 TO 4,000 UPH WITHIN ACCEPTABLE LOCATION PARAMETERS Mark Whiteside  Abstract
THE DEVELOPMENT OF A LOW COST WAFER LEVEL BUMPING TECHNIQUE Mark Whitmore et al.  Abstract
LASER ULTRASONIC INSPECTION OF FLIP CHIP UNDERFILL INTEGRITY Marvin Klein / Todd Murray and Thomas Steen  Abstract
TRENDS IN ALIGNED WAFER BONDING FOR MEMS AND IC WAFERLEVEL PACKAGING AND 3D INTERCONNECT TECHNOLOGIES Matthias Thorsten et al.  Abstract
LEAD-FREE AND TIN-LEAD ASSEMBLY AND RELIABILITY OF FINE PITCH WAFER LEVEL CSPs Michael Meilunas et al.  Abstract
WAFER LEVEL PACKAGE TEST STRATEGIES Paul Sakamoto and Alfred L. Crouch  Abstract
NOVEL SIP DESIGN CONCEPT: STACKED COPPER BGA Peter C. Salmon  Abstract
WAFER-LEVEL THREE-DIMENSIONAL ICs: A BETTER SOLUTION THAN SoCs AND SiPs? R.J. Gutmann, J.-Q. Lu and T.S. Cale  Abstract
LASER TECHNOLOGY FOR WAFER DICING AND MICROVIA DRILLING FOR NEXT GENERATION WAFERS Richard Toftness et al.  Abstract
ULTRASONIC FLIPCHIP BONDING - THE GREEN LOW COST ALTERNATIVE Roberto Gilardoni  Abstract
PLASMA STRESS RELIEF TECHNOLOGY Ryota Furukawa and Kazuhisa Arai  Abstract
ADVANCED IC PACKAGING MARKETS AND TRENDS Sandra Winkler and Steve Berry  Abstract
SURFACE PROPERTY CHARACTERIZATION OF PHOTO DIELECTRIC MATERIAL FOR WAFER LEVEL PACKAGING Shijian Luo and Tom Jiang  Abstract
WAFER-LEVEL BURN-IN AND TEST Steve Steps  Abstract
ELECTROLESS BUMPING FOR LOW K COPPER DEVICE TECHNOLOGY T. Teutsch, E. Zakel , T. Oppert  Abstract
LEAD vs LEAD-FREE: PACKAGING AND WAFER LEVEL CSP INFLUENCES Terence Q. Collier  Abstract
CHALLENGES AND DEVELOPMENTS IN WAFER LEVEL SOLDER INTERCONNECT Thomas Goodman and Peter Elenius  Abstract
WAFER LEVEL PACKAGE CHALLENGES - FABRICATION METHODOLOGY, PACKAGING INFRASTRUCTURE AND DIE-SHRINK CONSIDERATIONS Vern Solberg  Abstract
LEAD-FREE BUMPING AND ITS CHALLENGES Y. Zhang et al.  Abstract
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