International Wafer-Level Packaging Conference 2010 Proceedings

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TITLE AUTHOR
ENABLING COMPREHENSIVE AND EFFICIENT TEST OF 3D CHIPS BY STANDARDIZING THE TEST ACCESS ARCHITECTURE Al Crouch  Abstract
THE MEMS APPROACH FOR MAKING A LOW COST, HIGH SENSITIVITY MAGNETIC SENSOR Alan S. Edelstein, Greg A. Fischer, James E. Burnette and William F. Egelhoff, Jr.  Abstract
SCALABLE INTERCONNECT TECHNOLOGY THAT ENABLES HIGH DENSITY, HIGH PERFORMANCE AND LOW PROFILE CONNECTIVITY FOR BOARD TO BOARD, PACKAGE TO BOARD AND BOARD TO FLEX APPLICATIONS Amit Varma, Ming Wu and Charlie Stevenson  Abstract
WAFER LEVEL PROCESSING AND INTEGRATION TECHNIQUES FOR CMOS IMAGE SENSOR MODULE MANUFACTURING Bioh Kim, Thorsten Matthias, Gerald Kreindl, Viorel Dragoi, Markus Wimplinger, and Paul Lindner  Abstract
INTEGRATION OF ELECTROGRAFTED LAYERS FOR THE METALLIZATION OF DEEP TSVS C. Truzzi, S. Lerner, F. Raynal, V. Mevellec, N. Frederich, D. Suhr, I. Bispo and B. Couturier  Abstract
COST COMPARISON FOR FLIP CHIP, WIRE BOND, AND WAFER LEVEL PACKAGING Chet A. Palesko, Amy J. Palesko, and E. Jan Vardaman  Abstract
DEPTH MEASUREMENT OF THROUGH SILICON VIA BY USING IR CONFOCAL MICROSCOPE Deh-Ming Shyu, Wei-Te Hsu and Yi-Sha Ku  Abstract
WAFER BONDING PROCESS SELECTION E. Pabo, T. Tang, V. Dragoi, and T. Matthias  Abstract
MICROSPRINGS FOR INTEGRATED TEST AND PACKAGING Eugene M. Chow, Ph.D.  Abstract
NONDESTRUCTIVE CHARACTERIZATION OF CRITICAL FAILURES IN 3D INTEGRATIONS USING COMPUTED TOMOGRAPHY Gyujei Lee, Kang-won Lee, Hyun-joo Kim, Suk-woo Jeon, Kwang-yoo Byun, and Hae-bong Park  Abstract
WAFER LEVEL EMBEDDED SYSTEM IN PACKAGE (WL-ESiP) FOR 3D SiP SOLUTION In-Soo Kang, Gi-Jo Jung, Byoung-Yool Jeon, Jae-Hyouk Yoo and Byeung-Gee Kim  Abstract
LOW COST, HIGH DENSITY CHIP-LAYER VIAS FOR CHIPS-FIRST STACKED PACKAGES James E. Kohl, Ph.D., Charles W. Eichelberger, S. Keith Phillips, and Nancy G. Perkins  Abstract
COST EFFECTIVE WAFER LEVEL ENCAPSULATION FOR MEMS AND OTHER CIRCUIT ELEMENTS Jay Mitchell, Sangwoo Lee, Warren Welch, and Khalil Najafi  Abstract
FINE PITCH 3D DISPENSABLE ELECTRICAL INTERCONNECTS FOR SYSTEM IN PACKAGE SOLUTIONS Jeff S. Leal, Suzette K. Pangrle, Charles Whyte, Keith Barrie, Jeff Leff, Scott McGrath and Gerardo Ayala  Abstract
Cu PILLAR ELECTROPLATING PROCESS CONTROL FOR WAFER LEVEL PACKAGING Jim Zhang, Richard Hollman, Zhenqiu Liu and Arthur Keigler  Abstract
Wafer Bumping The Low Cost and Reliable Solution to Production Wafer Packaging John Mackay and Roger Gaw  Abstract
DEVELOPMENT OF AN EIGHT-DIE NAND LSOP PACKAGE Ke Xiao, Junfeng Zhao, Lefei Zhang, Mao Guo, Yong She, Yinglong Song, Eagle Lin, Dennis Chang, and MJ Chen  Abstract
FLIP CHIP DIE BONDING: AN ENABLING TECHNOLOGY FOR 3DIC INTEGRATION Keith A. Cooper, Michael D. Stead, Gilbert Lecarpentier, and Jean-Stephane Mottet  Abstract
HIGH VOLUME MANUFACTURING SOLUTION FOR WAFER LEVEL LENS MOLDING AND STACKING Kien Mun Lau, Michael Kast, Gerald Kreindl, Markus Wimplinger, Dominik Treiblmayr, Robert Breyer and Thorsten Matthias  Abstract
EXPLORATION OF MIGRATION AND STRESS EFFECTS IN POPS CONSIDERING INHOMOGENEOUS TEMPERATURE DISTRIBUTION L. Meinshausen and K. Weide-Zaage  Abstract
3D WAFER LEVEL PACKAGING OF MICRO CAMERA DEVICES Martin Wilke, Kai Zoschke, Julia Röder, Veronika Glaw, Michael Töpper, Ingrid Kuna, Karin Samulewicz, Oswin Ehrmann, Klaus-Dieter Lang and Herbert Reichl  Abstract
WAFER LEVEL PACKAGING: A FOUNDRY PERSPECTIVE Michael Shillinger  Abstract
DEMONSTRATION OF ULTRA-THIN SI GRINDING PROCESS CONTROLLED BY IN-SITU NON-CONTACT GAUGE FOR 3D STACKED IC (3D-SIC) Ming Zhao, Greet Verbinnen, Anne Jourdain, Eric Beyne, Bart Swinnen, Leonardus Leunissen, Tomotaka Tabuchi, Shinji Yoshida, and Susumu Hayakawa  Abstract
DESIGN METHODS FOR 3D IC INTEGRATION Peter Schneider, Sven Reitz, Jörn Stolle, Roland Martin, Andy Heinig and Andreas Wilde  Abstract
MECHANICAL BEHAVIOR MEASUREMENT OF SI WAFER Po-Yi Chang and Yi-Sha Ku  Abstract
TECHNOLOGY SOLUTIONS FOR A DYNAMIC AND DIVERSE WLCSP MARKET Ravi Chilukuri  Abstract
SINGLE SIDED WAFER THINNING FOR 3D INTEGRATION Ricardo I. Fuentes, Ph.D.  Abstract
SITE-SPECIFIC ANALYSIS OF ADVANCED PACKAGING ENABLED BY FOCUSED ION BEAMS (FIB) Richard J. Young, Chad Rue, Michael Schmidt, Ruud Schampers and David Wall  Abstract
MINIATURIZED WLP FOR MEMS Risto Mutikainen, Ph.D., Sami Nurmi, Ph.D., Tapani Alander, Ph.D., Esko Sirén, Lic. Tech. and Heikki Kuisma, M.Sc.  Abstract
ELECTRICAL, THERMAL AND MECHANICAL CHARACTERIZATION OF eWLB (EMBEDDED WAFER LEVEL BGA) Seung Wook Yoon, Meenakshi Prashant, Gaurav Sharma, Roger Emigh, Kai Liu, Sin Jae Lee, Ray Coronado, Yeong J. Lee, and Rajendra Pendse  Abstract
DEVELOPMENT OF NEXT GENERATION eWLB (EMBEDDED WAFER LEVEL BGA) PACKAGING Seung Wook Yoon, Yaojian Lin, Pandi Chelvam Marimuthu, Rajendra Pendse, Ganesh V. P, Andreas Bahr, Thorsten Meyer, Yonggang Jin, and Xavier Baraton  Abstract
RELIABILITY ANALYSIS OF 3D DISPENSABLE INTERCONNECTS FOR A SYSTEM IN A PACKAGE SOLUTION Suzette Pangrle, Jeff Leal, Scott McGrath, Grant Villavicencio, Keith Barrie, DeAnn Melcher, Sartaj Ajrawat, John Bray, Elizabeth Hankes, Jeff Leff, Elmer DelRosario, Marc Robinson, Sunil Kaul, Ken Holcomb, Catherine Shearer, Mark Kowalski, Anna Hall  Abstract
LAMINATE BASED FAN-OUT EMBEDDED DIE TECHNOLOGIES: THE OTHER OPTION Theodore (Ted) G. Tessier, Mark Dhaenens, David Clark, Tanja Karila, Tuomas Waris  Abstract
EWLB SYSTEM IN PACKAGE - POSSIBILITIES AND REQUIREMENTS Thorsten Meyer, Gerald Ofner, Christian Geissler and Klaus Pressel  Abstract
THE ENCAPSULATION OF MEMS/SENSORS AND THE REALIZATION OF MOLDED VIAS ON PACKAGE LEVEL AND WAFER LEVEL WITH FILM ASSISTED MOLDING Ton van Weelden and Lingen Wang  Abstract
3D SUBSTRATE INNOVATION FOR VERY FINE PITCH FLIP-CHIP APPLICATIONS Vern Solberg and Vage Oganesian  Abstract
EMBEDDED ACTIVE DEVICE PACKAGING TECHNOLOGY FOR REAL DDR2 MEMORY CHIPS Yin-Po Hung, Tao-Chih Chang, Ching-Kuan Lee, Yuan-Chang Lee, Jing-Yao Chang, Chao-Kai Hsu, Shu-Man Li, Jui-Hsiung Huang, Fang-Jun Leu, Yu-Wei Huang, Ren-Shin Cheng and Tai-Hong Chen  Abstract
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