International Wafer-Level Packaging Conference 2008 Proceedings

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TITLE AUTHOR
WLCSP PRODUCTION USING ELECTROLESS Ni/Au PLATING AND WAFER LEVEL SOLDER SPHERE TRANSFER TECHNOLOGY Andrew Strandjord, et al.  Abstract
3D DETECTOR TECHNOLOGY– WAFER BONDING AND DEEP REACTIVE ION ETCHING Angela Kok, et al.  Abstract
µPILR EMBEDDED PACKAGE TECHNOLOGY FOR MOBILE APPLICATIONS Carl Ryu, et al.  Abstract
VAPOR PHASE VS. CONVECTION REFLOW IN RoHS-COMPLIANT ASSEMBLY Chris Munroe  Abstract
VIAS LAST TECHNOLOGY FOR CMOS IMAGE SENSORS: PRESENTATION OF DESIGN RULES AND TECHNOLOGY David Henry, et al.  Abstract
A MARKET & TECHNOLOGY ANALYSIS OF WLP SOLUTION FOR ICs, CMOS IMAGE SENSORS & MEMS Eric Mounier, Ph.D., Jérôme Baron, and Jean-Christophe Eloy  Abstract
3D-WLCSP PACKAGE TECHNOLOGY: TECHNOLOGY AND DESIGN CONSIDERATIONS Eugene A. Stout, et al.  Abstract
WLCSP: CHALLENGES, PERFORMANCES AND TRENDS: KEY PARAMETERS INFLUENCING THE BOARD LEVEL RELIABILITY OF WLCSP Franck Dosseul, et al.  Abstract
APPLICATION OF Ni/Pd/Au SURFACE FINISHED SUBSTRATE FOR CHIP-SCALE PACKAGING AND ITS DROP TEST PERFORMANCE Geun Sik Kim, et al.  Abstract
COST REDUCTION OF WAFER LEVEL PACKAGING BY USING ESTABLISHED MATERIALS FROM NON-ELECTRONICS INDUSTRIES Giles Humpston  Abstract
LOW-COST COMPLIANT WAFER LEVEL PACKAGE TECHNOLOGY Guilian Gao, Kenneth Honer, and Charles Rosenstein  Abstract
RF CMOS CIRCUITS WITH WAFER-LEVEL PACKAGING INDUCTORS Hideki Hatakeyama, et al.  Abstract
A BASELINE STUDY ON THE PERFORMANCE OF STENCIL AND SCREEN PRINT PROCESSES FOR WAFER BACKSIDE COATING Jeff Schake  Abstract
NIR IMAGING OF BOND INTEGRITY FOR WAFER BONDING APPLICATIONS Jeremy McCutcheon, Louis McCarthy, and JoElle Dachsteiner  Abstract
METROLOGY IN WAFER-LEVEL MICROSPHERE PROCESSES Jim Hisert, Jeff Schake, and Paul Flynn  Abstract
NANOSPRAY – A NEW DEPOSITION METHOD FOR ISOLATING LAYERS FOR 3D TSV APPLICATIONS Johanna Bartel, et al.  Abstract
3D CHIP PACKAGING FOR CLASS I MEDICAL DEVICES John Dzarnoski, Ph.D. and Doug Link  Abstract
LITHOGRAPHIC CHALLENGES AND SOLUTIONS FOR 3D INTERCONNECT Keith Cooper, et al.  Abstract
SAPPHIRE WAFER-BASED WAFER-LEVEL CHIP SCALE PACKAGE TYPE HIGH POWER LIGHT-EMITTING DIODE Kwang Cheol Lee  Abstract
HIGH RATE ETCHING OF THROUGH SILICON VIAS FOR PACKAGING Leslie M. Lea  Abstract
HIGHLY IONIZED SPUTTERING FOR HIGH ASPECT RATIO THROUGH WAFER METALLIZATION M. Elghazzali, et al.  Abstract
INNOVATIVE FRONT TO BACK ALIGNMENT TECHNOLOGY FOR MEETING 3D PACKAGING REQUIREMENTS OF LEADING EDGE CONSUMER PRODUCTS Manish Ranjan, Emily True, and Andrew M. Hawryluk  Abstract
3D WAFER LEVEL PACKAGING TECHNOLOGY FOR CIS APPLICATIONS Marc Robinson  Abstract
TSV THINNED WAFER DEBONDING PROCESS OPTIMIZATION Mark Privett, et al.  Abstract
ALTERNATIVE METALIZATION TECHNOLOGIES FOR FLEXIBLE CIRCUITS AND DIFFICULT TO METALIZE SUBSTRATES Michael Carano  Abstract
VECTORED JETS IMPROVE CLEANING OF MICRO-ARRAY IC PACKAGES Mike Bixenman, DBA and Steve Stach  Abstract
INTEGRATED TESTING, MODELING AND FAILURE ANALYSIS OF CSPnl FOR ENHANCED BOARD LEVEL RELIABILITY Rex Anderson, et al.  Abstract
SEMICONDUCTOR PACKAGING SOLUTIONS UTILIZING FINE POWDER SOLDER PASTE Rick Lathrop  Abstract
NON-CAPILLARY PROTECTION OPTIONS FOR WLCSPs Russell Stapleton, Ph.D.  Abstract
METAL BASED WAFER LEVEL PACKAGING Shari Farrens, Ph.D.  Abstract
CMOS COMPATIBLE ELECTROLESS PLATING PROCESS FOR UNDER BUMP METALLIZATION Shigeo Hashimoto and Don Gudeczauskas, et al.  Abstract
SOLAR INTEGRATION TAKES A PAGE FROM THE SEMI WAFER CSP PLAYBOOK Steve T. Cho, Ph.D. and Steve Anderson  Abstract
INFRASTRUCTURE BUILDING FOR EMBEDDED DIE PRINTED WIRING BOARD APPLICATIONS Theodore G. Tessier, et al.  Abstract
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