International Wafer Level Packaging Conference 2007 Proceedings

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TITLE AUTHOR
ENABLING TECHNOLOGIES FOR APPLYING FLUIDS IN SEMICONDUCTOR PACKAGING Alec J. Babiarz and Horatio Quinones  Abstract
OPTIMIZATION OF A PHOTOSENSITIVE SPIN-ON DIELECTRIC PROCESS FOR COPPER INDUCTOR COIL AND INTERCONNECT PROTECTION IN RF SoC DEVICES Andrew Cooper and Alan Cuthbertson et al.  Abstract
STATE OF THE ART PROCESSING SCHEMES FOR BCB C.Brubaker and T. Matthias et al.  Abstract
AN ULTRA-THICK POSITIVE PHOTORESIST FOR ADVANCED ELECTROPLATING APPLICATIONS Chad Brubaker and Garrett Oakes et al.  Abstract
RELIABILITY OF A VOID FREE HYBRID NO-FLOW UNDERFILL PROCESS Daniel Baldwin and Michael Colella  Abstract
GEOMETRY AND BOND IMPROVEMENTS FOR WIRE BALL BONDING AND BALL BUMPING Daniel D. Evans, Jr.  Abstract
HERMETIC, WAFER LEVEL, CAVITY PACKAGE COMPATIBLE WITH COB ASSEMBLY G. Humpston et al.  Abstract
0.4 MM SOLDER BALL PITCH CHIP SCALE PACKAGING AND DROP TEST PERFORMANCE Geun Sik Kim and Dong Sik Kim  Abstract
LOW EXPANSION SUBSTRATES FOR WAFER-LEVEL PACKAGING OF OPTO- AND MEMS DEVICES Greg Rudd and Bud Kundich  Abstract
COMPLIANT WAFER LEVEL PACKAGE FOR ENHANCED RELIABILITY Guilian Gao and Bel Haba et al.  Abstract
PROSPECTIVE FUTURES FOR WAFERS, IC PACKAGES AND INTERCONNECTIONS Joseph Fjelstad  Abstract
THE INTEREATIONS BETWEEN SNAGCU SOLDER AND Ni(P)/Au, Ni(P)/Pd/Au UBMS Jui-Yun Tsai and Josef Gaida et al.  Abstract
CONFORMAL PHOTORESIST COATINGS FOR HIGH ASPECT RATIO FEATURES Keith A. Cooper and Clif Hamel et al.  Abstract
THE COMING PARADIGM SHIFT IN PACKAGING Ken Gilleo, Ph.D.  Abstract
IDENTIFYING DEFECTS AND DETERMINING ROOT CAUSES FOUND DURING THICK PHOTORESIST REMOVAL IN LEAD-FREE WLP Kimberly D. Pollard, Ph.D. and Raymond Chan, Ph.D.  Abstract
ENIG UBM WITH C4NP LEAD FREE SOLDER BUMPING Klaus Ruhmer and Eric Laine et al.  Abstract
ADVANCES IN FLIP CHIP UNDERFILL TECHNOLOGY FOR LEAD-FREE PACKAGING Larry Wang and Violet Evans et al.  Abstract
LAMINATION TECHNOLOGIES FOR SiP REALIZATION Lars Boettcher and Andreas Ostmann et al.  Abstract
DRIE ON 300 MM WAFERS FOR CSP AND SIP INTERCONNECTS Leslie Lea  Abstract
DEFORMABLE SILICON ELECTRONICS USING SEGMENTATION AND ULTRA-THIN SUBSTRATES M. Bartek and T. Zoumpoulidis et al.  Abstract
COPPER-PILLAR INTERCONNECT FOR FLIP-CHIP-ON-MODULE (FCOM) PACKAGING Mark Huang and Yong Poo Chia et al.  Abstract
CHIP PACKAGING 2.0 – USER DEFINABLE CHIP PINOUT PACKAGING FOR OPTIMIZED PC BOARD DESIGN Martin Hart  Abstract
FLUID FLOW STUDIES FOR REMOVING FLUX RESIDUE UNDER FLIP CHIP DIE Mike Bixenman  Abstract
DIE ATTACHMENT USING ELECTROPLATING FOR EMBEDDED CHIP PACKAGING PV Rainey and R Dickie et al.  Abstract
A PHOTOSENSITIVE, SPIN-APPLIED MASKING MATERIAL FOR THROUGH-SILICON VIA FORMATION FOR WAFER-LEVEL PACKAGING Ramachandran K. Trichur and Xie Shao  Abstract
NEW MATERIAL AND RELIABILITY ISSUES OF RE-DISTRIBUTION LAYERS Robert L. Hubbard  Abstract
ASSEMBLY PROCESS CHARACTERIZATION AND FAILURE ANALYSIS OF FLIP CHIP ASSEMBLIES USING NO-FLOW UNDERFILL Sangil Lee and Daniel F. Baldwin et al.  Abstract
HIGH PERFORMANCE BONDING SIMPLIFIES HIGH TECH 3D OPTIONS Shari Farrens, Ph.D.  Abstract
WAFER PLATING USING A SINGLE CHAMBER, MULTI-METAL, BUMP PLATING TOOL Steven Cho and Lee Levine  Abstract
WAFER-SCALE PACKAGING AND INTEGRATION ARE CREDITED FOR NEW GENERATION OF LOW-COST MEMS MOTION SENSOR PRODUCTS Steven Nasiri  Abstract
ULTRATHIN-WAFER PROCESSING UTILIZING TEMPORARY BONDING AND DEBONDING TECHNOLOGY Thorsten Matthias and Chad Brubaker et al.  Abstract
0.2MM BALL PLACEMENT FOR 0.3MM PITCH WAFER LEVEL CSPs Tom Falcon  Abstract
A RELIABLE WAFER-LEVEL CHIP SCALE PACKAGE (WLCSP) TECHNOLOGY Umesh Sharma and Philip Holland et al.  Abstract
µPILR™ PACKAGE-ON-PACKAGE QUALIFICATION TESTING A Practical 3D Solution for Memory and Mixed Memory Applications Vern Solberg  Abstract
3D PACKAGING AND INTERCONNECTING OF BARE DIE CHIPS BY DIRECT-PRINT TECHNOLOGY Vladimir Pelekhaty and Bo Li et al.  Abstract
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