International Wafer-Level Packaging Conference 2006 Proceedings

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TITLE AUTHOR
PATTERN EFFECTS ON ELECTROPLATED COPPER PILLARS Arthur Keigler, Bill Wu, Jim Zhang and Zhenqiu Liu  Abstract
SU-8 BONDING FOR TRANSPARENT PACKAGING C. Brubaker, T.Matthias and M. Wimplinger  Abstract
WAFER LEVEL STACKING OF 8 TO 10 DICE PER MM FOR CONSUMER PRODUCTS – WIRELESS DIE-ON-DIE “WDoD” Christian Val, Ph.D. and Pascal Couderc, Ph.D.  Abstract
EFFECTS OF PLASMA PRETREATMENT ON FLIP CHIP AND CSP SUBSTRATE LEVEL ASSEMBLY YIELD AND RELIABILITY Daniel Baldwin, Ph.D., Paul Houston and Brian Lewi  Abstract
METROLOGY FOR ULTRA-THIN WAFER AND DIE STRENGTH CHARACTERIZATION AND RELATED EDGE DAMAGE AND MODELING CHALLENGES David Liu, Anwei Liu, Michael I. Current, Wojtek J  Abstract
THE EXPANSION OF WAFER LEVEL PACKAGING: CHALLENGES AND OPPORTUNITIES E. Jan Vardaman  Abstract
C4NP - DATA FOR FINE PITCH TO CSP FLIP CHIP SOLDER BUMPING Eric Laine, Klaus Ruhmer, Luc Belanger, Michel Tur  Abstract
UTILIZATION OF DIE ATTACH ADHESIVES IN WAFER LEVEL ASSEMBLY OF CAVITY PACKAGES FOR IMAGE SENSORS G. Humpston, M. Nystrom, S. Kanagavel, M. Previti,  Abstract
AN INTEGRATED DEEP SILICON ETCH/ DIRECTIONAL PHYSICAL VAPOR DEPOSITION PROCESS FOR THROUGH-WAFER VIA APPLICATIONS G. Reynolds, C. Constantine, S. Lai, K. Mackenzie,  Abstract
CHALLENGES IN FLIP CHIP DIE SORTING, HANDLING AND INSPECTION Gerald Steinwasser  Abstract
PLACING WAFER LEVEL DEVICES IN A HIGH SPEED WORKFLOW Gheorghe Pascariu  Abstract
LITHOGRAPHY-GRADE CONTROLLED EXPANSION SUBSTRATES FOR WAFER LEVEL PACKAGING Greg Rudd and Bob Cronk  Abstract
FABRICATION OF TAPERED THROUGH-VIAS ON (100) SILICON FOR WAFER-LEVEL PACKAGING Huang Shuang Wu and Chia Yong Poo  Abstract
HYBRID WAFER-LEVEL PACKAGING FOR RF-MEMS APPLICATIONS J. Iannacci, M. Bartek, J. Tian, S. Sosin, A. Akhn  Abstract
SQUEEGEE INFLUENCE ON BUMP METRICS FOR STENCIL PRINTED WAFERS Jeff Schake and Guy Burgess  Abstract
STAIR-STEP IC PACKAGES FOR LOW COST AND HIGH PERFORMANCE Joseph Fjelstad  Abstract
STUDY OF Ni-P/Pd/Au AS A FINAL FINISH FOR WAFER Kazuki Yoshikawa, Toshiaki Shibata, Masayuki Kiso,  Abstract
OVERVIEW OF MEMS WAFER LEVEL PROCESSES AND PATENTS Ken Gilleo, Ph.D.  Abstract
WHITE RING DEFECT FORMATION IN LEAD-FREE WAFER LEVEL PACKAGING Kimberly D. Pollard, Ph.D., Raymond Chan, Ph.D., a  Abstract
SiP – IDENTIFYING ISSUES FOR STACKED (3D) MULTICHIP PACKAGING ADOPTION Larry Gilg  Abstract
DRIE WITH HIGH RATE AND UNIFORMITY FOR MEMS AND WLP Leslie Lea  Abstract
EMBEDDED IC POLYIMIDE MULTI-LAYER SUBSTRATE M. Okamoto, S. Ito, S. Okude, T. Suzuki, O. Nakao,  Abstract
AEROSOL-JET PRINTING FOR 3-D INTERCONNECTS, FLEXIBLE SUBSTRATES AND EMBEDDED PASSIVES Martin Hedges, Mike Kardos, Bruce King, and Mike R  Abstract
NON LITHOGRAPHIC MICROCELL PLATING FOR INTEGRATED PASSIVES AND RDL P. Moller, M. Fredenberg, P. Leisner, M. Ostling  Abstract
COPPER PANEL FABRICATION AND STACKING CONCEPT FOR VLP FB DIMMS Peter C. Salmon  Abstract
BCB WAFER BONDING WITH ELECTRICAL INTERCONNECTS Praveen Pandojirao-S, Rachita Dewan, Dan O. Popa,  Abstract
FORMATION OF LEAD-FREE MICROBUMPS BY ELECTROPLATING FOR FLIP-CHIP AND WLP APPLICATIONS R. Kiumi, F. Kuriyama, N. Saito  Abstract
USING THE 2D MACRO CD METROLOGY PACKAGE TO MEASURE CD LINES Rajiv Roy, Matt Wilson, and Chris Hawes  Abstract
RF CROSSTALK SUPPRESSION BASED ON WAFER-LEVEL PACKAGING CONCEPT S.M. Sinaga, A. Polyakov, M. Bartek, and J.N. Burg  Abstract
THE IC PACKAGING WORLD AND ITS LATEST DEVELOPMENTS Sandra L. Winkler  Abstract
ADVANCED PLASMA PROCESSING TECHNIQUES FOR IMPROVING DESCUM AND OTHER WLP PROCESS PERFORMANCE Scott D. Szymanski  Abstract
STUDY ON ADHESION OF DICING DIE ATTACH TWO-IN-ONE FILM FOR 3-D STACK PACKAGING Shijian Luo, Ph.D. and Tom Jiang, Ph.D.  Abstract
ADVANCED PACKAGE PROTOTYPING USING NANO-PARTICLE SILVER PRINTED INTERCONNECTS Sungchul Joo and Daniel F. Baldwin, Ph.D.  Abstract
SURFACE CLEANING FLIP CHIP WAFERS FOR TEST AND ASSEMBLY IMPROVEMENTS Terence Collier  Abstract
WAFER-LEVEL PACKAGING: EFFECTIVE COST REDUCTION WITH WAFER BONDING Thorsten Matthias, Markus Wimplinger and Paul Lind  Abstract
WAFER-TO-WAFER AND CHIP-TO-WAFER INTEGRATION SCHEMES FOR SYSTEMS-IN-A-PACKAGE AND 3D INTERCONNECTS Thorsten Matthias, Stefan Pargfrieder, Herwig Kirc  Abstract
METHODOLOGY FOR STACKING OF POWER SEMICONDUCTORS FOR THE HARSH AUTOMOTIVE ENVIRONMENT Todd P. Oman  Abstract
UTCP : 60 µm THICK BENDABLE CHIP PACKAGE W. Christiaens, B. Vandevelde, E. Bosman, and J. V  Abstract
ASSEMBLING OPTICAL DEVICES UTILIZING WAFER LEVEL TECHNOLOGY AND CHIP ON BOARD PROCESS TO ENABLE HIGHER YIELDS AND REDUCED COSTS Yehudit Dagan, Giles Humpston, and Michael J. Nyst  Abstract
SINGLE WAFER BUMPING Yixiang Xie, Qiang Fu, and Solomon Basame  Abstract
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