Journal of SMT Article

ADVANCEMENTS IN STACKED CHIP SCALE PACKAGING (S-CSP), PROVIDES SYSTEM-IN-A-PACKAGE FUNCTIONALITY FOR WIRELESS AND HANDHELD APPLICATIONS

Author: Morihiro Kada
Company: Sharp Corporation
Date Published: 4/1/2000   Volume: 13-2

Abstract: To achieve continuous size, weight and cost reductions, wireless handset manufacturers and their semiconductor suppliers have been developing new semiconductor devices and packaging technologies that enable high levels of functional integration at the smallest most cost effective level, which is through silicon (Si) integration. The high levels of Si integration for baseband functions have come the quickest due the system level integration nature of ASICs (Application Specific IC) and the common CMOS processing for baseband functions. The memory and RF functional integration for cellphones is currently being accomplished through application specific packaging advancements or System-in-a-Package (SiP) technologies. This is due to the complications of integrating different IC technologies or densities in a single chip or System-on-a-Chip (SoC) solution. This paper will look at advancements in Stacked CSP (S-CSP) technology that allow further system integration of diverse device technologies including: Flash, SRAM and DRAM memory as well as baseband, mixed signal and logic functions. Stacked chip package integration, will be critical to allow the torrid pace of handset size, weight and cost reductions to continue.



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