Journal of SMT Article

A COMPARISON BETWEEN POWER AND THERMAL CYCLING FOR A FC PBGA

Authors: Andrew Mawer, D. Hodges Popps, and G. Presas
Company: Motorola Semiconductor
Date Published: 1/1/2004   Volume: 17-1

Abstract: Ball grid array (BGA) component to board interconnection reliability has traditionally been characterized by thermal cycling with controlled constant ramp rates and dwell times at various extremes, depending on the end application [1, 2].

At any point within the thermal cycle, the motherboard, component, and solder joints are all at approximately the same temperature. In actual electronic systems, individual component temperature distributions are the result of both the heating of the air internal to the system by all components and the local heat dissipation of that component. The local heating portion can be significant, especially for high power devices, and it can result in large thermal gradients within the package and between the package and board. Although it is more involved and difficult to control than thermal cycling, power cycling, where power is applied to the packaged die, is one way of better simulating actual system thermal gradients [2-7].

This paper will describe comparative power versus thermal board-level cycling performed on a 119 pin flip chip (FC) PBGA test vehicle between room temperature and 125°C. The solder joints were continuously monitored until >50% failures. The custom system, which provided closed loop control to each device under test to minimize variability amongst the samples, will be described in detail. Failure modes and statistics will also be detailed.



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