Journal of SMT Article

RELIABILITY ASSESSMENT OF FLIP CHIP ON LAMINATE CSP

Authors: Julia Y. Zhao, Ph.D.
Company: Analog Devices
Date Published: 7/1/2002   Volume: 15-3

Abstract: In recent years, various new product applications have pushed wire bond technology to its electrical performance limits, and flip chip interconnection has emerged as a major packaging solution for high performance, low power, small form factor, and good thermal performance.

Despite the long-time existence of flip chip, for each specific product and package application it remains a challenging task to select the right materials and right technology for optimized performance and reliability at comparatively low cost. In fact, alternative materials and process technologies for flip chip remain open areas of investigation to meet newer product challenges, which in turn motivates studies on new failure mechanisms and design optimization.

There is also a need for industry standards for testing and characterizing packages with flip chip technology. This paper presents a case study of reliability assessment of a low cost flip chip on laminate CSP for embedded DSP application. A daisy-chained test die was packaged in both molded and exposed die forms. Parametric studies included die thickness and passivation materials. Failure mechanisms, design and assembly factors are discussed.

Key words: Flip chip, laminate, CSP, reliability, failure analysis, failure mechanism, warpage measurement, die thinning, underfill, polyimide.



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