Journal of SMT Article


Author: James Rathburn
Company: Gryphics, Inc.
Date Published: 4/1/1999   Volume: 12-2

Abstract: The increasing popularity of chip scale packaging (CSP) has presented some challenges to those involved in the test and burn-in industry. Users who must test and burn-in CSPs face many considerations when trying to implement a practical solution. The functional requirements differ dramatically between functional test and burn-in applications. An informal study was conducted evaluating the relevant performance parameters for each type of commercially available socket relative to the requirements of each application.

This paper is intended to provide insight into the issues related to evaluating the proper approach for these operations. An interesting conclusion regarding the technologies generally available in the marketplace will also be addressed.

The introduction of CSP devices into the electronics industry has been met with much publicity and promise for opportunity. As with all new packing styles, these devices bring challenges with their potential benefits. To date, the majority of CSPs fitting the official definition fall within the memory- or space-sensitive product areas. Early introductions seem to be in high-volume, cost-sensitive applications.

This situation is beneficial from an early adoption standpoint, but is also a detriment, since these product lines are dependent upon a cost-efficient infrastructure. As the semiconductor industry continually evaluates the need for test and burn-in, the companies supporting those operations must identify how they can make practical implementation less painful. Since test adds no value to a part, less painful usually means higher performance with lower cost of ownership or use.

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