Journal of SMT Article


Authors: Paul P.E. Wang, Ph.D.1, DongJi Xie, Ph.D4., Michae
Company: 1 XBOX, Microsoft Corporation; 2 Taiwan Semiconduc
Date Published: 4/1/2007   Volume: 20-2

Abstract: Increasing demands for graphic virtual reality and computation speed on gaming devices are pushing the process units from the current 90nm transistors into 65nm transistors. To make a stride in reducing the problem of power leakage and improving the core performance in clock cycle, new chip design strategy and process technology are required.

In this study, a product specific technical consortium is initiated by voluntary participants, including OEM, Chip Supplier, Soldering Material, Fab Supplier, EMS, and Metallurgical/Failure Analytical Lab to study the FCBGA thermal and mechanical reliability. A 65nm FCBGA with electrical daisy chain and thermal die is included in a Test Vehicle (TV) and Box Emulator (BE). To facilitate and streamline the design development cycle, a closed loop Design for Reliability (DFR) model is proposed.

Finite Element Analysis (FEA) was performed on a test board with almost the same probing pin-out to see the strain response on the PCB by correlating to gage the measurement. Then the strain level of the solder joint was benchmarked to the yield strength. The reliability of FCBGA-solder-PCB pad interconnect system was real-time monitored during Accelerated Thermal Cycling (ATC) in order to assess the interconnect fatigue life and failure mode. In order to derive the mechanical residual stress correlation to the reliability scale, a four-point bending test fixture was used to apply levels of stress before ATC was conducted on the stressed interconnect system. Finite Element Modeling was performed to study the strain level in the solder interconnect to provide insight for fatigue life estimation. Extensive metallurgical analysis was conducted at time zero as well as during the ATC to reveal solder crack growth, intermetallic compound evolution and interfacial grain structure.

The thermal interconnect management system, Process Unit-Thermal Interface Material-Heatsink-Fan, contained in the Box Emulator, is used to derive the die junction temperature (Tj) and thermal resistance (Rth) at various interconnect interfaces. Thermal degradation of the system, particularly the Thermal Interface Material (TIM), is also assessed by thermally stressing the system in ATC then plotting the Tj and Rth variation in time series.

Key words: closed loop Design for Reliability, residue stress, life testing, reliability, 65nmy

Cost to download:

  Members: Free! (Log on to receive the member rate)
  Non-Members: $10

Why become an SMTA member?

Not a member yet? Join SMTA today!

Notice: Sharing of articles is prohibited. Downloaded papers must only be stored on a local hard drive and not in a shared repository either internal or external.


SMTA Headquarters
6600 City West Parkway, Suite 300
Eden Prairie, MN 55344

Phone 952.920.7682
Fax 952.926.1819
Site Map
Update Your Info
Related Links
Send Us Feedback
Contact Us
Privacy Policy
↑ Top