A STUDY OF THE FAILURE MECHANISMS IN LEAD-FREE AND EUTECTIC TIN-LEAD SOLDER BUMPS FOR FLIP CHIP ASSEMBLY
Authors: Julia Y. Zhao, David Mackessy, and John Jackson Company: Analog Devices Incorporated Date Published: 4/1/2006
Abstract: Flip chip solders of composition 95.5Sn/4Ag/0.5Cu (SAC) and 63Sn/37Pb (SnPb) were compared in package level reliability testing. Bumping processes using electroplating and screen printing were also compared. Bump fatigue resistance, solid state isothermal aging, and temperature humidity performance were monitored using Automated Test Equipment (ATE) for resistance measurement of a daisy-chain test die assembled in a flip chip BGA package. Daisy chain resistance changes monitored during High Temperature Storage (HTS) were compared to shear strength changes. The effect of thermal aging on bump fatigue performance was evaluated; shear strength did not directly reflect fatigue resistance. Bump degradation monitored as an increase in the daisy-chain resistance was correlated to Intermetallic Compound (IMC) morphology changes and crack growth during temperature cycling testing (TCT). For material selection studies, HTS is recommended as a precursor to TCT. For Pb-free bumps the dominant failure mechanism was found to be brittle fracture between the solder and IMC near the under bump metallurgy (UBM). Crack segments developed at the edge of the UBM as well as in the middle between IMC and solder. Underfill materials need to be carefully selected to optimize TCT performance.