Journal of SMT Article


Authors: Lars Boettcher, A. Neumann, A. Ostmann and H. Reichl
Company: Fraunhofer Institute for Reliability and Microinte
Date Published: 4/4/2006   Volume: 19-2

Abstract: The coming generations of portable products require significant improvement of the packaging technologies, mainly due to increasing signal frequencies and the demand for higher density of functions. State of the art is organic substrate with micro via build-up layers, equipped on both sides with discrete passive and active components. The space requirement of active chips can be already reduced to a minimum by implementing CSP´s (chip size packages) or flip chips. A further miniaturization however requires a 3-dimensional integration of active and passive components. Additionally the signal frequencies will increase to several GHz in high speed digital applications. In order to maintain signal integrity, much shorter and impedance-matched interconnects between chips and passive components are required. In this paper a new approach will be described which allows both extreme dense 3-dimensional integration and very short interconnects. This approach, called “Chip in Polymer” is based on the integration of thin components into build-up layers of printed circuit board. Beside the process technology this paper will emphasize on the needed wafer preparation.
Keywords: 3D packaging, embedded chips, Chip in Polymer

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