Journal of SMT Article

DESIGN ANALYSIS AND OPTIMIZATION OF WAFER-LEVEL CSP BOARD LEVEL SOLDER JOINT RELIABILITY

Author: Tong Yan Tee et al.
Company: STMicroelectronics
Date Published: 7/1/2005   Volume: 18-3

Abstract: For wafer-level chip scale package (WLCSP), board level solder joint reliability during thermal cycling test is a major concern. This is because underfill is usually not applied in the board assembly process. This paper focuses on the design optimization of WLCSP for improved solder joint reliability performance with fatigue modeling. Both global and local 3D parametric fatigue models are established for WLCSP with considerations of detailed pad design, realistic shape of solder bump, and non-linear material properties.

The fatigue model applied is based on a modified Darveaux's approach with non-linear viscoplastic analysis of solder joints. A solder joint damage model is used to establish a connection between the strain energy density (SED) per cycle obtained from the FEA model and the actual characteristic life of solder joint during thermal cycling test. The modeling predicted fatigue life is first correlated to the thermal cycling test results using modified correlation constants. Subsequently, design analysis is performed on 11 design parameters.

Finally, six critical design parameters, i.e. solder bump standoff, maximum solder bump diameter, UBM opening size, PCB pad size, PCB in-plane CTE, and die thickness, are selected to optimize the package for better solder joint reliability performance. The interaction of different design parameters is also studied, and the combined effect of UBM opening size and PCB pad size has the strongest influence on solder joint reliability. Besides, the fatigue life is observed to vary linearly with die size. The optimized design can improve the fatigue life by more than two times and extend the die size limit of the WLCSP package from 3.2 x 3.2mm to 7 x 7mm.

Key words: wafer-level CSP, fatigue, modeling, solder joint reliability.



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