Journal of SMT Article


Authors: R. Tummala, A. Aggarwal, S. Bansal, and P.M. Raj
Company: Georgia Institute of Tech.
Date Published: 7/1/2005   Volume: 18-3

Abstract: As the ICs approach nanoscale with more than 10,000 I/Os, it is becoming clear that current assembly methods, such as wire bonding and solder interconnects, pose insurmountable pitch, reliability and electrical performance barriers. Wafer-level packaging with conventional substrates and solders fail due to poor fatigue resistance at 20-50 micron pitch. Compliant structures have too high an inductance and electrical resistance.

Nano-interconnects provide an opportunity to have the best of both electrical and mechanical properties, in addition to low cost and at-speed test and burn-in benefits not presently available. The electrical performance with nano-interconnect approaches is expected to reach that of bumpless/chip-first interconnection technologies while enabling low-cost reworkability at the same time.

This paper examines current assembly technologies at microscale and the emerging nanoscale interconnect technology that can provide the best electrical and mechanical performance with unlimited I/Os.

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