Journal of SMT Article

SURFACE MOUNT CERAMIC CHIP CAPACITOR RELIABILITY IN A HIGH VOLTAGE ENVIRONMENT

Authors: Frank Liotine, Jr.
Company: Raytheon Systems Company
Date Published: 7/1/1999   Volume: 12-3

Abstract: Higher packaging densities have resulted in many technical challenges, some of which have proven to place opposing requirements on several parameters when considering the balance between low cost assembly versus a high reliability application. For example, when using large leadiess ceramic chip capacitors, good design practice suggests placing the chips on matched substrates in order to minimize stress, e.g. ceramic boards or some form of a compensated circuit board technology. However, given the need to maintain low cost, both on the manufacturing floor and in the end product, a standard epoxy-glass board may be selected as the substrate of choice. The possibility of high thermal coefficient of expansion (TCE) differences between the chip capacitor and the circuit card needs to be addressed in order to assure long-term reliability, especially where high voltage conditions are present.

The ramifications of large TCE differences can lead to substrate damage; however, the predominant failure mechanism will be ceramic chip capacitor cracking within the matrix of the capacitor dielectric [11]. Differential TCE concerns will be further exaggerated during thermal shock, either during production test screening or during actual product operation if severe environments are present [13]. Coupled with this will be the electrical effects generated by higher voltages where such conditions are part of the circuit operation. Each of these issues will reflect upon the potential long-term reliability or product life.

The demand to promote lower product and production cost usually implies the use of low cost substrates such as G-10 or G-12 epoxy based boards. High-density designs demand the use of ceramic chip capacitors, especially in higher voltage situations. Consequently, the issues of stress relief, electrical performance, and long term reliability must be adequately modeled in order to assure proper design and long term performance.

When these parameters are combined with the demands for cost effective manufacturing they appear to conflict, and, in fact, they may indeed be at opposite ends of the design guide. However, the ultimate issue or design goal is to maintain the internal stress levels within the ceramic dielectric; below that of the materials' rupture modulus.

Key Words: ceramic chip capacitor, leadless surface mount component, dielectric crack, thermal coefficient of expansion, high voltage, solder joint long-term reliability.



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