Workshops

Tuesday, June 6, 2017

WS1: Shining a Light on LED Technology: Construction, Reliability, Qualification, Failure Modes Process Material

WS2: The Incredible Shrinking World Of Electronics – Are Traditional DFM, DFR, DFF, ... Methods Obsolete?

WS3: Understanding Shock & Vibration

WS4: DFX- Design for Cleaning and Reliability Excellence


WS1: Shining a Light on LED Technology: Construction, Reliability, Qualification, Failure Modes

M. Simard-Normandin, Ph.D., MuAnalysis Inc.
June 6, 2017 | 8:30am - 12:00pm

Course Objectives:
Light emitting diodes, LEDs, have evolved tremendously in the last few years. They are no longer relegated to such roles as low output power indicator lights on panels, or seasonal decorative light strings. Just as electronics has infiltrated every aspect of our lives, a LED invasion is aggressively underfoot. Yet the technology behind these devices is poorly understood, often leading to avoidable early failures. In this workshop we will look at every aspect of LED technology. First we will explore the semiconductor devices themselves and the structures within that allow them to be efficient emitters. Next we will focus on high brightness LEDs and review their packaging and assembly challenges. Then we will investigate LEDs in luminaires: the phosphor materials of the LED devices, LED driving circuits, dimming issues. Finally, the long term reliability issues and failure mechanisms of LED devices will be reviewed.

Topics Covered:

Introduction

  • What are LEDs
  • History
  • LEDs in applications


  • LED device structure
  • Direct vs indirect band gap
  • Single junction vs hetero-junction
  • Device structure
  • Quantum wells and super lattices
  • Doping
  • Contact metallurgy
  • Growth substrates


  • LED Packaging
  • Heat dissipation
  • Lens types
  • Phosphors
  • Wire bonded and flip chip LEDs
  • Light distribution
  • Comparison of different manufacturers


  • LED reliability
  • LED measurements
  • Radiant and luminous intensity
  • Viewing angles
  • CRI


  • LED Qualification
  • Standards
  • Test procedures
  • Life time


  • LED failure modes
  • Performance
  • Catastrophic vs degradation
  • Package vs die failures
  • Power supply failures
  • Martine Simard-Normandin

    About the Instructor:
    Dr. Simard-Normandin has over 30 years experience in microelectronics, specializing in semiconductor device physics, reverse engineering and electrical and material characterization. She has authored or co-authored more than 50 scientific journal and conference papers on microanalysis. Dr. Simard-Normandin holds a B.Sc. in physics from the Université de Montréal, a M.Sc. and Ph.D. in astronomy from the University of Toronto. She was awarded an Industrial Postdoctoral Fellowship from the American Physical Society, focusing on microelectronics, and recently the prestigious Medal of the Faculty of Arts and Sciences of the Université de Montréal. Dr. Simard-Normandin has held the positions of Manager - Materials and Device Analysis at STMicroelectronics’ Centre for Microanalysis and Manager of Materials and Structures Analysis at Nortel Networks. In 2002 she founded MuAnalysis Inc., a privately-owned Canadian company offering expertise in failure analysis, materials analysis and reliability testing.




    WS2: The Incredible Shrinking World Of Electronics – Are Traditional DFM, DFR, DFF, ... Methods Obsolete?

    Dale Lee, Plexus Corp.
    June 6, 2017 | 8:30am - 12:00pm

    Course Overview:
    Today's electronic component packaging technologies of smaller packages (0201/01005/008003), finer lead pitch (0.4/0.35/0.3/...), bottom terminated components (QFN/LGA) and printed circuit board designs (high layer counts, finer lines, via in pad (VIP), increased copper thicknesses, copper routing, ...), increased thermal sensitivity, trailing component, fabrication and assembly industry standards have impacted traditional assembly processes with addition of tight solder application, component placement, thermal management and soldering constraints. Using traditional, simplified mass production techniques may not be sufficient to achieve a high-yielding manufacturing process. This presentation will highlight elements of the impacts of these technologies on reliability and yield when not properly addressed in the design/assembly/inspection-test process, impacts of thermal connections on through-hole and surface soldering processes, introduce the elements of design for matched process (DFMP), and provide examples of several opportunities within the DFMP for yield improvement through manufacturing tooling design, SMT and PTH assembly process matching. The concept of manufacturing, test, reliability by design (XBD) will be presented.

    What you will learn:

  • Component packaging impacts
  • PCB design impacts and industry standards limitations
  • SMT and PTH solder design impacts
  • Components with thermal management impacts:
      1) Component design
      2) PCB Thermal balance: X, Y and Z axis
      3) Trace routing
      4) Equipment limitation/tolerance
      5) PCB array tolerance
      6) Process tooling design
  • Process control impacts
  • Paste volume, thermal shock SMT and PTH, reflow process warpage
  • Cleaning impacts
  • Compatibility issues, low stand-off components

    Dale Lee

    About the Instructor:
    Dale is a Senior Staff DFX Strategy Engineer with Plexus Corporation primarily involved with DFX analysis, root cause failure analysis and definition/correlation of design, process, legislative and tooling impacts on assembly processes and manufacturing yields. Dale has been involved in surface mount design, package & process development and production for over twenty years in various technical and managerial positions. These activities have included research, development and implementation of advanced manufacturing technologies and interconnect techniques, design and development of CSP & BGA packages, PCB & PCBA support, DFM/DFX analysis of flex, rigid-flex & rigid PCB/PCBA's including supply chain, process qualification and new process introduction for domestic and foreign low, medium and high volume production applications. Dale has authored, instructed and presented frequently on topics including advanced SMT packaging, PCB and SMT design, assembly, cleaning, DFM/DFX and rework. He is a past recipient of the Surface Mount Technology Association's "Excellence in Leadership" award. He has been very involved with multiple industry associations and activities including SMTA, IPC, PERM, SMCBA and INEMI.




    WS3: Understanding Shock & Vibration

    Alec Feinberg, DfR Soft
    June 6, 2017 | 1:30pm - 5:00pm

    Course Overview:
    This 4-hour tutorial will start with the basics, defining such terms as “G”, “g”, “GRMS” and “G-Force”. We will explain the details of shock and vibration in understandable terms. At the end of this course the student will be able to clearly understand shock and vibration, its terms, how tests are specified, and have the capability to apply software as a test aid. This tutorial will work with excel based software to aid in quickly learning shock and vibration fundamentals. We will talk about the different kinds of shock, discuss constant acceleration, sine vibration and random vibration. By the end of the tutorial you will be able to understand, specify many tests and perform a number of analyses.




    WS4: Design for Cleaning and Reliability Excellence

    Dale Lee, Plexus Corp.
    June 6, 2017 | 1:30pm - 5:00pm

    Course Overview:
    Design complexities and functionality requirements are continually decreasing spacing between PCB conductors and component packages pins. As devices decrease in size and stand-off height, contamination trapped between leads or under component package body can lead to unavoidable and unwanted intermittent or catastrophic malfunctions. Contamination trapped under components can result in electro-chemical migration, leakage currents and stray capacitance in an electronic circuit due to high voltage and frequency.

    Cleaning is used on many designs to mitigate these issues. However, very little to no considerations during the product development process are allocated to address the cleaning process. Cleaning process is almost always a throw it over the wall issue for manufacturing to address as part of their process design. Factors such as the density of components, component layout, thermal heat requirements, and standoff height/clearance are key considerations. This presentation will address design methodologies and process changes to PCB assembly designs to improve the ability to remove flux residues, improve cleanliness from under passive, BGA and low stand-off component packages (DFN, QFN, LGA, etc.) to improve reliability of soldered electronic assembly.

    Dale Lee

    About the Instructor:
    Dale is a Senior Staff DFX Strategy Engineer with Plexus Corporation primarily involved with DFX analysis, root cause failure analysis and definition/correlation of design, process, legislative and tooling impacts on assembly processes and manufacturing yields. Dale has been involved in surface mount design, package & process development and production for over twenty years in various technical and managerial positions. These activities have included research, development and implementation of advanced manufacturing technologies and interconnect techniques, design and development of CSP & BGA packages, PCB & PCBA support, DFM/DFX analysis of flex, rigid-flex & rigid PCB/PCBA's including supply chain, process qualification and new process introduction for domestic and foreign low, medium and high volume production applications. Dale has authored, instructed and presented frequently on topics including advanced SMT packaging, PCB and SMT design, assembly, cleaning, DFM/DFX and rework. He is a past recipient of the Surface Mount Technology Association's "Excellence in Leadership" award. He has been very involved with multiple industry associations and activities including SMTA, IPC, PERM, SMCBA and INEMI.









  • Cancellation Policy: Registration fees will be refunded (less a $75 processing fee) if written notice is postmarked two weeks prior to the event date. Cancellations received within two weeks prior to event date will not be refunded to cover costs incurred.