Wednesday, October 7th, 2020 @ 8:30am-12:00pm (US Pacific)
Presenter: Vern Solberg, Vern Solberg Consulting
This course addresses the design and assembly challenges for developing and implementing flip-chip and multiple function System-in-Package (SiP) technology. Although integrating several semiconductor functions onto a single die element (System-on-Chip) appears to provide a viable solution for some, development cost and time has often proved to be excessive. On the other hand, many companies have realized that wafer level packaging (WLP, FOWLP, FOPLP) and integrating mature multiple-die elements into a 2D or 3D configured package actually proves to be superior to the multiple function die concepts because it minimizes risk, significantly reduces development time and cost.
The material presented has been developed to better enable the product designer and manufacturing specialist to evaluate a broad number of semiconductor packaging methodologies. The examples shown will furnish both physical and monetary benefits gained using multiple die packaging as well adverse concerns related to supply-chain obstacles and infrastructure limitations.
- BGA/CSP Process Technologies and Standards - Single Die BGA and FBGA Packaging - Flip-Chip and Die Size Package Technologies - Wafer Level Packaging (WLP) - Fan-Out Wafer level Packaging (FOWLP) - JEDEC Package Outline Standards
- Innovative Solutions for 2D, 2.5D and 3D Packaging - 2D BGA Package Technology - 3D Multiple Die and Stacked Package Methodologies - Implementing 2.5D for High Density BGA Applications - Silicon Based Interposer Structures - Glass Based Interposer Structures - Organic (Laminate) Based Interposer Structures
- Printed Circuit Board Design Guidelines for HDI - Ball Grid Array (BGA) - Fine Pitch Ball Grid Array (FBGA and DSBGA) - Flip-Chip (WLP/FOWLP) - 2.5D Interposer structures
- HDI Circuit and Micro Via Design Implementation - HDI Circuit Fabrication Variations - Micro Via Process Methodology - Design Guidelines for HDI Circuits - HDI Sources and Economic Issues
- Specifying PCB Base Material, Surface Finish and Coatings - Organic base material selection criteria - Specifying thickness of copper foils - Surface plating and coating variations - Solder mask process considerations
- Preparation for High Volume Assembly Processing - Surface Mount Assembly Process Overview - Basic features needed for SMT assembly processing - System requirements for BGA and CSP device placement - Palletizing to maximize assembly process efficiency - Assembly process implimentation
WHO SHOULD ATTEND:
This coarse will benefit PCB Designers, Design Engineers and those responsible for semiconductor package and electronic product development, assembly processing and manufacturing efficiency as well as manufacturing and test engineering specialists for the OEM, ODM, EMS and OSATs (Outsourced Assembly and Test) providers.
ABOUT THE INSTRUCTOR:
Vern Solberg is an independent consultant specializing in SMT and microelectronics design and manufacturing technology. He has served the industry for more than thirty years in areas related to both commercial and aerospace electronic products and is active as an author and educator.
Vern has served IPC as chairman and co-chair in developing the current IPC 7900 series standards, is a recipient of the SMTA Founders Award, IPC Presidents Award, the Raymond E. Pritchard Hall of Fame Award and holds several patents for IC packaging innovations including the folded-flex 3D package technology. In addition to developing numerous technical papers and PCB designer focused magazine columns, Solberg is the author of Design Guidelines for Surface Mount and Fine-Pitch Technology a McGraw-Hill publication.