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Implementing TSV for 3D Semiconductor Packaging

Presenter: Vern Solberg
Company: STC Madison
Date Published: 8/16/2012

Description: Overview:
The current market driver for semiconductor package technology is to provide more functionality and improve performance without increasing package size. Vertically configured 3D package technology addresses this issue for a broad number of enterprise products. Initially, the 3D package contained two or more semiconductor die elements mounted on top of one another most often interconnected using a common substrate interposer. Adapting through silicon via (TSV) technology for die-on-die interface on the other hand has the potential to further improve both package performance and package assembly efficiency. Progress in this area has accelerated through the cooperation and joint development programs between a number of government, industry and technical universities. An early high volume application for TSV was for the small CMOS image sensors used in wireless handsets to enable the vertical joining of the sensor and related logic element.

Although the TSV process is touted as the 'next big thing' in semiconductor packaging, capabilities and methodologies for providing wafers and die elements for stacking currently vary a great deal between suppliers. Although TSV technology has the potential to revolutionize semiconductor packaging, it currently remains hostage to a very limited homogeneous family of products; MEMS, memory and image sensors. In addition, there are a number of processes and methodologies that are considered proprietary and may require licensing agreements and additional fees for their use. Industry roadmaps, however, continue to point toward the eventual use of TSV in developing new generations of high performance system-in-package products.

What You Will Learn:
This webinar will explore two basic approaches to TSV formation, via-first and via-last: Via-first integration forms very small via holes in the wafer during front-end processing. Via-last integration may occur before or after bonding wafers or joining individual die elements to one another (Die-on-Die). Due to the increased thickness of pre-joined die, the via-last process typically provides somewhat larger via holes than the via-first variation.

Who Should View This Webinar:
This Webinar has been developed specifically for product and circuit design professionals, systems engineers as well as assembly and test engineering specialists for OEM, ODM and EMS providers.

About the presenter:
Vern Solberg is a technical consultant for Invensas Corporation specializing in SMT and microelectronics design and manufacturing technology. Vern is a US delegate to the JISSO International Council (JIC) and is currently an active member of IEEE, SMTA, IMAPS and the IPC. He has served the industry for more than thirty years in areas related to both commercial and aerospace electronic products and is active as an author and educator. Solberg holds several patents for 3D semiconductor packaging innovations and is the author of Design Guidelines for Surface Mount and Fine-Pitch Technology and furnishes the 'Designers Notebook' column for SMT magazine.

Key Words: 

TSV, via-first, via-last, Die-on-Die



Pricing:
  Members: $0.00 (Log on to receive the member rate)
  Non-Members: $75.00



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