International Wafer-Level Packaging Conference 2006 Proceedings

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    TITLE AUTHOR DOWNLOAD
    PATTERN EFFECTS ON ELECTROPLATED COPPER PILLARS Arthur Keigler, Bill Wu, Jim Zhang and Zhenqiu Liu  Purchase 
    SU-8 BONDING FOR TRANSPARENT PACKAGING C. Brubaker, T.Matthias and M. Wimplinger  Purchase 
    WAFER LEVEL STACKING OF 8 TO 10 DICE PER MM FOR CONSUMER PRODUCTS – WIRELESS DIE-ON-DIE “WDoD” Christian Val, Ph.D. and Pascal Couderc, Ph.D.  Purchase 
    EFFECTS OF PLASMA PRETREATMENT ON FLIP CHIP AND CSP SUBSTRATE LEVEL ASSEMBLY YIELD AND RELIABILITY Daniel Baldwin, Ph.D., Paul Houston and Brian Lewi  Purchase 
    METROLOGY FOR ULTRA-THIN WAFER AND DIE STRENGTH CHARACTERIZATION AND RELATED EDGE DAMAGE AND MODELING CHALLENGES David Liu, Anwei Liu, Michael I. Current, Wojtek J  Purchase 
    THE EXPANSION OF WAFER LEVEL PACKAGING: CHALLENGES AND OPPORTUNITIES E. Jan Vardaman  Purchase 
    C4NP - DATA FOR FINE PITCH TO CSP FLIP CHIP SOLDER BUMPING Eric Laine, Klaus Ruhmer, Luc Belanger, Michel Tur  Purchase 
    UTILIZATION OF DIE ATTACH ADHESIVES IN WAFER LEVEL ASSEMBLY OF CAVITY PACKAGES FOR IMAGE SENSORS G. Humpston, M. Nystrom, S. Kanagavel, M. Previti,  Purchase 
    AN INTEGRATED DEEP SILICON ETCH/ DIRECTIONAL PHYSICAL VAPOR DEPOSITION PROCESS FOR THROUGH-WAFER VIA APPLICATIONS G. Reynolds, C. Constantine, S. Lai, K. Mackenzie,  Purchase 
    CHALLENGES IN FLIP CHIP DIE SORTING, HANDLING AND INSPECTION Gerald Steinwasser  Purchase 
    PLACING WAFER LEVEL DEVICES IN A HIGH SPEED WORKFLOW Gheorghe Pascariu  Purchase 
    LITHOGRAPHY-GRADE CONTROLLED EXPANSION SUBSTRATES FOR WAFER LEVEL PACKAGING Greg Rudd and Bob Cronk  Purchase 
    FABRICATION OF TAPERED THROUGH-VIAS ON (100) SILICON FOR WAFER-LEVEL PACKAGING Huang Shuang Wu and Chia Yong Poo  Purchase 
    HYBRID WAFER-LEVEL PACKAGING FOR RF-MEMS APPLICATIONS J. Iannacci, M. Bartek, J. Tian, S. Sosin, A. Akhn  Purchase 
    SQUEEGEE INFLUENCE ON BUMP METRICS FOR STENCIL PRINTED WAFERS Jeff Schake and Guy Burgess  Purchase 
    STAIR-STEP IC PACKAGES FOR LOW COST AND HIGH PERFORMANCE Joseph Fjelstad  Purchase 
    STUDY OF Ni-P/Pd/Au AS A FINAL FINISH FOR WAFER Kazuki Yoshikawa, Toshiaki Shibata, Masayuki Kiso,  Purchase 
    OVERVIEW OF MEMS WAFER LEVEL PROCESSES AND PATENTS Ken Gilleo, Ph.D.  Purchase 
    WHITE RING DEFECT FORMATION IN LEAD-FREE WAFER LEVEL PACKAGING Kimberly D. Pollard, Ph.D., Raymond Chan, Ph.D., a  Purchase 
    SiP – IDENTIFYING ISSUES FOR STACKED (3D) MULTICHIP PACKAGING ADOPTION Larry Gilg  Purchase 
    DRIE WITH HIGH RATE AND UNIFORMITY FOR MEMS AND WLP Leslie Lea  Purchase 
    EMBEDDED IC POLYIMIDE MULTI-LAYER SUBSTRATE M. Okamoto, S. Ito, S. Okude, T. Suzuki, O. Nakao,  Purchase 
    AEROSOL-JET PRINTING FOR 3-D INTERCONNECTS, FLEXIBLE SUBSTRATES AND EMBEDDED PASSIVES Martin Hedges, Mike Kardos, Bruce King, and Mike R  Purchase 
    NON LITHOGRAPHIC MICROCELL PLATING FOR INTEGRATED PASSIVES AND RDL P. Moller, M. Fredenberg, P. Leisner, M. Ostling  Purchase 
    COPPER PANEL FABRICATION AND STACKING CONCEPT FOR VLP FB DIMMS Peter C. Salmon  Purchase 
    BCB WAFER BONDING WITH ELECTRICAL INTERCONNECTS Praveen Pandojirao-S, Rachita Dewan, Dan O. Popa,  Purchase 
    FORMATION OF LEAD-FREE MICROBUMPS BY ELECTROPLATING FOR FLIP-CHIP AND WLP APPLICATIONS R. Kiumi, F. Kuriyama, N. Saito  Purchase 
    USING THE 2D MACRO CD METROLOGY PACKAGE TO MEASURE CD LINES Rajiv Roy, Matt Wilson, and Chris Hawes  Purchase 
    RF CROSSTALK SUPPRESSION BASED ON WAFER-LEVEL PACKAGING CONCEPT S.M. Sinaga, A. Polyakov, M. Bartek, and J.N. Burg  Purchase 
    THE IC PACKAGING WORLD AND ITS LATEST DEVELOPMENTS Sandra L. Winkler  Purchase 
    ADVANCED PLASMA PROCESSING TECHNIQUES FOR IMPROVING DESCUM AND OTHER WLP PROCESS PERFORMANCE Scott D. Szymanski  Purchase 
    STUDY ON ADHESION OF DICING DIE ATTACH TWO-IN-ONE FILM FOR 3-D STACK PACKAGING Shijian Luo, Ph.D. and Tom Jiang, Ph.D.  Purchase 
    ADVANCED PACKAGE PROTOTYPING USING NANO-PARTICLE SILVER PRINTED INTERCONNECTS Sungchul Joo and Daniel F. Baldwin, Ph.D.  Purchase 
    SURFACE CLEANING FLIP CHIP WAFERS FOR TEST AND ASSEMBLY IMPROVEMENTS Terence Collier  Purchase 
    WAFER-LEVEL PACKAGING: EFFECTIVE COST REDUCTION WITH WAFER BONDING Thorsten Matthias, Markus Wimplinger and Paul Lind  Purchase 
    WAFER-TO-WAFER AND CHIP-TO-WAFER INTEGRATION SCHEMES FOR SYSTEMS-IN-A-PACKAGE AND 3D INTERCONNECTS Thorsten Matthias, Stefan Pargfrieder, Herwig Kirc  Purchase 
    METHODOLOGY FOR STACKING OF POWER SEMICONDUCTORS FOR THE HARSH AUTOMOTIVE ENVIRONMENT Todd P. Oman  Purchase 
    UTCP : 60 µm THICK BENDABLE CHIP PACKAGE W. Christiaens, B. Vandevelde, E. Bosman, and J. V  Purchase 
    ASSEMBLING OPTICAL DEVICES UTILIZING WAFER LEVEL TECHNOLOGY AND CHIP ON BOARD PROCESS TO ENABLE HIGHER YIELDS AND REDUCED COSTS Yehudit Dagan, Giles Humpston, and Michael J. Nyst  Purchase 
    SINGLE WAFER BUMPING Yixiang Xie, Qiang Fu, and Solomon Basame  Purchase 

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