Journal of SMT Article
SOLDER JOINT RELIABILITY OF ChipArray BGA
Company: Amkor Technologies
Date Published: 4/1/1999 Volume: 12-2
While chip scale and near chip scale packages offer the advantage of small size and increased packaging density, the solder joint reliability of these packages can become a concern for some applications. Although smaller package size reduces the DNP (distance from neutral point) effect, the relatively large chip-to-package area ratio causes the effective CTE of the package to be closer to that of silicon, thus resulting in greater CTE mismatch with the motherboard.
Higher densities are also driving the ball pitch down, which in turn results in smaller pads and smaller solder balls connecting the package to the motherboard. These factors cause reduction in fatigue life so that a package may not be able to meet 2nd level reliability requirements.
This paper investigates these factors for the ChipArray package. Thermal cycle test data is presented for a 0.5 and a 0.8mm pitch package for two test conditions and motherboard thicknesses. Since it becomes cost prohibitive and impractical to study the effect of a number of different design variables through tests, the effect of package size, die size, motherboard thickness, substrate thickness, and test conditions are quantified using a life prediction approach.
*ChipArray is a trademark of Amkor Technologies
Cost to download:Members: Free! (Log on to receive the member rate)
Not a member yet? Join SMTA today!
Notice: Sharing of articles is prohibited. Downloaded papers must only be stored on a local hard drive and not in a shared repository either internal or external.