Abstract: Based on the electroless wafer-level redistribution technology, the development of a rerouting technology for vertical power transistor devices, which includes the wiring through a via in the silicon wafer from the back to the front side, was realized. The basic technology approaches, as well as the stencil printing of preformed solder balls, will be presented and discussed.
In this paper the development of a three-dimensional wafer-level redistribution process based on fully additive metal deposition will be presented. This technology uses a photosensitive epoxy material which was designated for the formation of sequential built up layers for printed circuit boards, and electroless copper, nickel and gold deposition, for the realization of the conductor lines [1, 2, 3, 4]. A brief overview of the process features will be presented in the paper in order to provide the fundamental knowledge for process understanding.
As a new development, the three-dimensional re-routing of a contact pad from the back side to the front side will be presented. For the realization of this connection, a via is drilled in the silicon wafer using a UV laser. To enable an electroless metal deposition it is necessary to isolate the wall of the via with a suitable material, which also provides the ability to realize a good adhesion of the subsequently deposited copper. The evaluation of various epoxy materials to realize the isolation layer, as well as different methods, will be presented and discussed. The formation of the conductor lines will be described, and first results will be presented.
The last technology step for the realization of vertical power devices involves the solder balling of the redistributed wafer pads. The placement of lead-free balls with a size selected based on the resultant pitch of the 3D redistributed conductor line pads will be described.
Key words: wafer-level redistribution, 3D, epoxy dielectric, CSP, electroless metallization, 3D metallization, laser drilling, via-in-via, solder balling.