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Chapter News

Low-Temperature Solders

Date: Wednesday March 22, 2017

Time: 4:30PM-7:00PM

Venue: Axiom Electronics

Address: 19545 NW Von Neumann Drive, Beaverton, OR 97006

 

The transition to Pb-free solders in electronics began in the early 1990s as a follow-on to the elimination of Pb-bearing solders from potable water systems and food handling equipment (1986).  The objective was to develop a single alloy having solidus and liquidus temperatures that were equal to, or less than, the eutectic temperature of the 63Pb-37Pb solder.  Three alloy development efforts were undertaken by Sandia Laboratories either as standalone projects or as a participant in one of the following partnerships: (1) U.S. Army, Redstone Arsenal (Huntsville, AL); (2) AT&T Engineering Research Center (AT&T/ERC, Princeton, NJ), and (3) National Center for Manufacturing Sciences (NCMS, Ann Arbor, MI).   The soldering technology data, which were developed from these efforts, were in three general categories: (a) existing, very low melting temperature solders 52In-48Sn (In-Sn) and 97In-3Ag (In-Ag); (b) development of the Sn-Ag-Bi solder (largest effort); and (c) the creation of non-Pb alloy compositions that achieved melting temperatures equivalent to eutectic Sn-Pb solder.  The In-Sn and In-Ag solders continue to find niche applications in optoelectronics and sensor products.  A materials and modeling database was developed for these solders as a toolset for predicting solder joint reliability.  The most widely-studied alloy is the 91.84Sn-3.33Ag-4.83Bi solder having the solidus temperature of 212°C.  Materials data included solderability testing to support process development activities as well as intermetallic compound (IMC) growth behavior and Pb contamination data necessary for predicting solder joint reliability.  The temperature cycling of printed wiring assembly (PWA) test vehicles provided TMF test data while materials properties data supported the computational models for predicting TMF.  The discussion will wrap up with a brief analysis of the Pb-free solder composition having solidus temperature (Ts) equivalent to that of the eutectic Sn-Pb alloy: 66Sn-5.0Ag-10Bi-5.0Au-10In-4.0Cu alloy, Ts = 178°C.  This material exhibited good solderability on Cu with a contact angle of 34.2+0.7°.  The physical metallurgy principles will be discussed that were used to develop this and similar, Sn-based, very low melting temperature solders.

 

[1] Sandia is a multiprogram laboratory operated by Sandia Corporation, a Lockheed Martin Company, for the United States Department of Energy’s National Nuclear Security Administration under Contract No. DE-AC04-94AL85000.

Paul T. Vianco received a Ph.D. degree in Materials Science from the University of Rochester (New York) in 1986. He joined Sandia National Laboratories, Albuquerque, New Mexico in 1987 where he is currently a distinguished member of the technical staff.  Paul has been involved in all aspects of packaging interconnection technology: materials, processing, and reliability. Paul is a fellow of the American Welding Society (AWS) and ASM, International. He is also the author of the Soldering Handbook – Third Edition (2000) and Guideline for Hand Soldering Practices (2016), both of which are published by the AWS.






Improve SMT Assembly Yields Using Root Cause Analysis in Stencil Design

Date: Monday Feb 27, 2017
Time: 4:30PM-7:00PM
Venue: Axiom Electronics
Address: 19545 NW Von Neumann Drive, Beaverton, OR 97006


Reduction of first pass defects in the SMT assembly process minimizes cost, assembly time and improves reliability.  These three areas, cost, delivery and reliability determine manufacturing yields and are key in maintaining a successful and profitable assembly process.   It’s commonly accepted that the solder paste printing process causes the highest percentage of yield challenges in the SMT assembly process.  As form factor continues to get smaller, the challenge to obtain 100% yield becomes more difficult.   This paper will identify defects affecting SMT yields in the printing process and discuss their Root Cause.   Outer layer copper weight and surface treatment will also be addressed as to their effect on printability.  Experiments using leadless and emerging components will be studied and root cause analysis will be presented on the following common SMT defects: 

  • Poor Solder Paste Release:  Focus will be placed on small components

  • Solder-balls (Mid Chip Solder Beads): Stencil design to minimize solder balls

  • Tombstoning: Improving tombstoning with stencil design

  • Bridging at Print: Simple guidelines to eliminate bridging

  • Insufficient Solder Volume at SMT Reflow: Look at the correlation of stencil design to solder volume after reflow

  • Bridging at SMT Reflow: What causes bridging after reflow when it is not present after print

  • Voiding:  Design ideas to reduce voiding through stencil design

This paper summarizes the results of this study with respect to the variables tested.  Root Causes of these challenges will be identified and practical stencil design recommendations will be made with the intent of eliminating defects and improving yields during the printing process.   

 

                                                

                Tony Lentz has worked in the electronics industry since 1994.  He worked as a process engineer at a circuit board manufacturer for 5 years.  Since 1999, Tony has worked for FCT Companies as a laboratory manager, facility manager, and most recently a field application engineer.  Since 2013, Tony has focused on field application and R&D for FCT Assembly solder and stencil products.  Tony has extensive experience doing research and development, quality control, and technical service with products used to manufacture and assemble printed circuit boards.  He has published and presented many papers at industry events.  Tony holds B.S. and M.B.S. degrees in Chemistry.  

[Update] Link to presented material:
http://www.smta.org/chapters/files/Oregon_Chapter_2017-02_Improve_SMT_Assembly_Yields_Using_Root_Cause_Analysis.pdf


 






SMTA Certification

 SMT Processes- August 15-17, 2017 (Portland, OR)

                Now available in Oregon!

 

·        August 15- Course (8:30-5pm)

·        August 16- ½ day of course + exam

·        August 17- All day exam (8:30-5pm)


Instruction: English 
Test: English 
Instructor: Jim Hall, ITM Consulting

               For more information, http://www.smta.org/certification/






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Chapter Calendar of Events
Date / Time Event Location Phone Contact/Email
January 18, 2017
4:30 pm
Understanding PCB Design & Material Warpage Challenges BiAmp 503-696-1542   Pedro J Martinez 
pedro.j.martinez@intel.com
February 27, 2017
04:30 pm
Improve SMT Assembly Yields Using Root Cause Analysis in Stencil Design Axiom Electronics, LLC 503-696-4072   Pedro J Martinez 
pedro.j.martinez@intel.com
March 22, 2017
4:30 pm
Low Temperature Solders; Processing and Reliability TBD 5036961542   Pedro J Martinez 
pedro.j.martinez@intel.com
April 19, 2017
08:30 am
Chapter Training Day : Defect Analysis & Process Trouble Shooting Axiom 5036961542   Pedro J Martinez 
pedro.j.martinez@intel.com
April 19, 2017
Oregon Defect Resolution Chapter Tutorial Program Axiom Electronics   Karen Frericks 
May 10, 2017
Expo - Oregon 2017 Tektronix Building   Dave Larson 
August 15, 2017
Certification - SMT Processes - August 15-17 (Portland, OR) - -   Jenny Ng 
August 15, 2017
08:30 am
SMT Processes Certification Course TBD 952-920-7682   Jenny Ng 
jenny@smta.org


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Our Chapter Leaders

President : Alexander Schreiner  (Newson USA LLC)
Phone : 503-758-6491
Email : alex.schreiner@frontier.com

Vice President : Pedro J. Martinez  (Intel Corporation)
Phone : 503-696-1542
Email : pedro.j.martinez@intel.com

Treasurer : Daniel J. Yantz  (Milwaukee Electronics)
Phone : 503-263-7301
Email : dyantz@milwaukeeelectronics.com

VP of Technical Programs : Charles E. Bauer Ph.D.  (TechLead Corporation)
Phone : 303-674-8202
Email : chuck.bauer@techleadcorp.com

VP of Membership : James L Mills  (Vanguard EMS)
Phone : 503-672-4303
Email : james.mills@vanguard-ems.com

Events Coordinator (Appointed) : Ruth A. Conner  (RAD Services)
Phone : 503-819-4895
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Email : michael.brinkley@axiomsmt.com

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Phone : 503-750-7740
Email : ayman.a.fayed@intel.com

CTP Committee (Appointed) : Scott K. Buttars  
Phone : 503-314-5478
Email : scott.k.buttars@gmail.com

Board Liaison : Raiyo Aspandiar (Intel Corporation)
Phone Contact : 503-696-2627
Email Address : raiyo.f.aspandiar@intel.com

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Global Participating Members of our Chapter

Micro Systems Engineering, Inc.

NCAB Group



Corporate Members of our Chapter

Ascentec Engineering

Ascentron, Inc

Axiom Electronics LLC

CheckSum

ControlTek

Dorigo Systems Ltd.

ECD

Garmin AT, Inc.

Hi-Rel Laboratories

Hi-Tek Electronics

Intel Corporation

Micro Systems Engineering, Inc.

Pentagon EMS Corporation

Prototron Circuits

Quality Production Ltd.

Reliable Controls Corporation

Surtek Industries Inc.

Tektronix, Inc.

VersaLogic Corporation



SMTA Global Members

Amazon Celestica Inc. Cisco Systems, Inc. Creation Technologies Inc. FCA Group Harris Corporation Henkel Electronic Materials LLC HISCO, Inc. IDENTCO Jabil Circuit Sdn. Bhd. Keysight Technologies KYZEN Sdn. Bhd. Metallic Resources, Inc. Micro Systems Technologies Management AG Microsoft Corporation NCAB Group USA NEO Technology Solutions Plexus Corp. Samtec Microelectronics SMAC Specialty Coating Systems Vexos Vitronics Soltec USA ZESTRON Americas

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